DESIGN AND FPGA IMPLEMENTATION OF OFDM SYSTEM
Abstract
In this thesis, a baseband OFDM system with channel estimation and timing synchronization is designed andimplemented using the FPGA technology. The system is prototyped based on the IEEE 802.11a standard and the
signals is transmitted and received using a bandwidth of 20 MHz. With the help of the quadrature phase shift keying
(QPSK) modulation, the system can achieve a throughput of 24 Mbps. Moreover, the least squares (LS) algorithm is
implemented and the estimation of a frequency-selective fading channel is demonstrated. For the coarse estimation
of timing, a modified maximum-normalized correlation (MNC) scheme is investigated and implemented. Starting
from theoretical study, this thesis in detail describes the system design and verification on the basis of both
MATLAB simulation and hardware implementation. Bit error rate (BER) verses bit energy to noise spectral density
(Eb/N0) is presented in the case of different channels. In the meanwhile, comparison is made between the simulation
and implementation results, which verify system performance from the system level to the register transfer level
(RTL).
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